The present invention relates to a technique for inspecting a semiconductor device, and particularly to a technique effective for application to a substrate-type semiconductor device.
Japanese Patent Laid-open No. 2005-229137 (Patent Document 1) discloses, for example, a technique in which a central part of the substrate of a ball grid array semiconductor device is warped, in such a manner to project in the direction of the plane opposite to the plane mounted with the semiconductor chip, so as to electrically couple the electrode on the mounting substrate with solder bumps.
Moreover, Japanese Patent Laid-open No. 2009-277971 (Patent Document 2), for example, discloses a technique to find a warp deformation amount showing a warp deformation state of a component with bumps, compare the warp deformation amount with a preset threshold, and determine whether the warp deformation state of the component with bumps is satisfactory.
[Patent Document 1]
Japanese Patent Laid-open No. 2005-229137
[Patent Document 2]
Japanese Patent Laid-open No. 2009-277971